1. Technical Field
Embodiments of the present disclosure relate generally to testing of integrated circuits, and more specifically to providing enhanced control in scan tests of integrated circuits with partitioned scan chains.
2. Related Art
Scan-based tests (scan tests) are often performed to test integrated circuits (IC). A scan test generally refers to a test approach in which storage elements (e.g., flip-flops) in an IC are connected as a scan chain, a test vector is shifted into the scan chain via input test pins provided on the IC, the IC is placed in an evaluation mode (capture phase) to cause the inputs to be evaluated, and a corresponding response vector obtained in the capture cycle is shifted out via output test pins. The bit values in the response vector are compared with an expected output to determine any fault conditions in the IC.
ICs are often designed with partitioned scan chains, implying that each partitioned scan chain contains a corresponding set of storage elements which are operable as a scan chain to receive a corresponding test vector. Partitioned scan chains are used for reasons such as testability of desired set of partitions in isolation, operability of different partitions in different frequencies, power management, etc., as is well known in the relevant arts.
It is generally desirable that more control be provided in such environments so that tests suitable in corresponding environments may be employed.